FIELD OF THE INVENTION
The invention relates to a circuit configuration for triggering or driving a power FET connected in series with a load on the source side and coupled to a supply voltage terminal on the drain side, having a charge pump supplying an output signal fed to a gate terminal of the power FET, a depletion-mode FET with a load path through which a gate-source capacitance of the power FET can be discharged, and a device for triggering the charge pump and the depletion-mode FET.
Such a circuit configuration is disclosed in U.S. Pat. No. 5,352,932. That patent discloses, for example in FIG. 1, a circuit which on one hand has a charge pump, and on the other hand has a device for rapidly turning off the power FET. If, in accordance with FIG. 1, a switch 12 is turned on, then an FET 5 and thus a bipolar transistor 8 are switched on. As a result, the power FET 1 is also switched on and the latter remains switched on since the gate voltage is increased by the necessary value due to a square-wave signal at a terminal 11. The switch 12 is opened for the purpose of turn-off, as a result of which the depletion-mode FET 16 is switched on and the gate-source capacitance of the power FET is consequently discharged.
That known circuit has the following disadvantage: in the event of an overcurrent, that is to say when there is a low-impedance load, the gate voltage of the power FET 1 is held at approximately the Zener voltage of a Zener diode 15 when a voltage drop between a supply voltage terminal 3 and a load terminal 4, that is to say the drain-source path of the power FET 1, is large. Since the gate-source voltage across a depletion-mode FET 16 assumes a small value in that case, the depletion-mode FET 16 is switched on and consequently draws the current of the charge pump for as long as it remains switched on. That produces a dip in the limited switch-on peak current. Such a dip is disadvantageous particularly in the case of a lamp switch, where very high switch-on peak currents occur.